The following circuit schematic diagram is used to convert a low-voltage PWM signal into an amplified and buffered linear output. It is designed for fan speed control. This converter uses PWM outputs to control fan speed as a function of temperature.

A PMOS FET (Q2) and a pair of BJTs (Q1) are used as a linear amplifier. The base of PNP in Q1 acts as the non-inverting input to the amplifier and the emitter of the NPN is the inverting input. The PNP is biased as an emitter follower and the NPN is used as the initial gain an as an emitter follower. The two input voltages approximately track each other because the NPN and PNP operate at roughly the same temperature and current density. The amplifier output is the VGS of Q2 that is amplified at Q2′s drain because of the drop across R2. The output offset of the amplifier primarily is about 100mV because the drop across R3 forces the VGS threshold of Q2. This circuit allows a 3.3V input to provide linear control of a 12V fan.
The cutoff frequency must be selected to reduce the PWM ripple at the output, 1 / [6.28 * R * C], at least two decades below the PWM. Due to high impedance of the circuit led to the use of a resistor value as high as 100k. [source : maxim-ic.com]